FIG. 1 is a diagram showing the entire structure of a plasma display device (PDP device). A reference numeral 10 denotes a plasma display panel (PDP). While there are various types of PDPs, any type of the PDP has at least two or more sets of plural electrodes arranged in parallel, and scan pulses are sequentially applied to a set of plural electrodes. The present invention relates to the drive circuit for driving plural electrodes to which scan pulses are applied. In the following description, a triple-electrode type PDP device of an address/display separation method which is now widely used will be described as an example.
In the PDP 10, a first substrate and a second substrate are attached to each other and discharge gas is injected therebetween. On the first substrate, a plurality of first (X) electrodes and a plurality of second (Y) electrodes are alternately arranged in parallel to each other, which are covered with a dielectric layer. On the second substrate, a plurality of address (A) electrodes are arranged in parallel to each other in the direction perpendicular to the X and Y electrodes, barrier ribs are provided between the address electrodes, and phosphors are coated on the address electrodes and the side surfaces of the barrier ribs. Display cells C are formed at the positions where the X and Y electrodes intersect the address electrodes.
The display is performed by applying a high voltage to each electrode to generate a discharge between the electrodes. For this reason, the PDP device is provided with an X electrode drive circuit 11 for applying the voltage to the X electrodes, and a Y electrode drive circuit 12 for applying the voltage to the Y electrodes, and an address electrode drive circuit 13 for applying the voltage to the address electrodes.
In the PDP device, only the on/off control whether the light is emitted or not can be performed, and it is difficult to control luminous intensity. Hence, in order to perform a grayscale display, one display frame is divided into a plurality of sub-fields, and the grayscale display is performed by combining the sub-fields to be lit.
FIG. 2 is a diagram showing an example of driving waveforms applied to each electrode in one sub-field in the PDP device of FIG. 1. Each sub-field has basically the same sequence, but is different in the length of sustain discharge period and the number of sustain pulses applied in the sustain discharge period.
As shown in FIG. 2, the sub-field includes a reset period in which all the cells are brought into a uniform state, an address period in which the cells to be turned on are selected, and the sustain discharge period in which the selected cells are turned on.
In the reset period, 0 V is applied to the address electrodes and a positive voltage +Vs is applied to the Y electrodes. In this state, the voltage gradually lowering from 0 V to a negative voltage is applied to the X electrodes. Thereafter, in the state where the negative voltage is applied to the X electrodes, the voltage increasing from the positive voltage to Vw is applied to the Y electrodes. In this manner, a wall charge is formed on the dielectric layers of all the cells. This operation is referred to as a reset write, and the voltage increasing from the positive voltage to Vw which is applied to the Y electrodes is referred to as a reset write pulse. Then, after the voltage +Vs is applied to the X electrodes and the voltage applied to the Y electrodes is set to 0V, the voltage gradually decreasing to −Vs is applied to the Y electrodes. Accordingly, the wall charges formed in all the cells are almost erased. This operation is referred to as a reset erase, and the voltage gradually lowering from 0 V to −Vs, which is applied to the Y electrodes, is referred to as a reset erase pulse. Note that the final voltage of the reset erase pulse (in this case, −Vs) relates to the amount of residual wall charge. Since the voltage to be applied for the next address discharge can be decreased by leaving some amount of wall charges, the final voltage of the reset erase pulse is appropriately set.
In the address period, in the state where the voltage +Vs is applied to the X electrodes and a voltage Vsc is applied to the Y electrodes, the scan pulse of a voltage −Vy is sequentially applied to the Y electrodes, and the address pulse of a voltage Va is applied to the address electrodes of the cells to be turned on in accordance with the application of the scan pulses. By doing so, address discharges are generated between the Y electrodes and the address electrodes of the cells to which the scan pulse and the address pulse are applied at the same time, and the discharge acts as a trigger to generate the address discharges between the X electrodes and the Y electrodes of the cells. Accordingly, negative wall charges are formed on the dielectric layer of the X electrodes, and positive wall charges are formed on the dielectric layer of the Y electrodes. The wall charge is not formed in the cell in which the address discharge is not generated. When the scan pulses are sequentially applied to all the Y electrodes to perform such an operation, the cells to be turned on are selected from all the cells.
In the sustain discharge period, first, when the sustain pulse of −Vs is applied to the X electrodes and the sustain pulse of +Vs is applied to the Y electrodes, the voltage by the wall charge is superposed to generate the sustain discharge in the cells where the address discharge has been generated, and a positive wall charge is formed on the dielectric layer of the X electrodes and a negative wall charge is formed on the dielectric layer of the Y electrodes, thereby completing the initial sustain discharge. Since the wall charge is not formed in the cell where the address discharge is not generated, the sustain discharge is not generated. Next, when the sustain pulse of +Vs is applied to the X electrodes and the sustain pulse of −Vs is applied to the Y electrodes, the voltage by the wall charge is superposed to generate the sustain discharge in the cell where the previous sustain discharge is generated, and a negative wall charge is formed on the dielectric layer of the X electrodes, and a positive wall charge is formed on the dielectric layer of the Y electrodes. Subsequently, by applying the sustain pulses to the X electrodes and the Y electrodes while changing the polarity, the sustain discharge is continued.
In the driving waveforms shown in FIG. 2, the positive and negative voltages are applied to the X electrode and the Y electrode. Before the use of the driving waveforms shown in FIG. 2 was started, the sustain pulse of 2Vs was applied to only one of the X electrode and the Y electrode to generate the sustain discharge. For example, when Vs is 90 V, 2Vs is 180 V. To realize a power supply circuit capable of generating such a high voltage, it is necessary to use a driving element with a high withstand voltage on the other hand, when the driving waveforms shown in FIG. 2 are used, the size of the power supply circuit can be reduced.
Further, in the driving waveforms shown in FIG. 2, in the reset period, the pulses in which the voltage gradually changes are applied to the X electrodes and the Y electrodes. Before the use of the driving waveforms shown in FIG. 2 was started, the pulses in which the voltage rapidly changes were applied. Consequently, a large discharge was generated in all the cells in the reset period, and as a result, all the cells emitted light with high intensity and the display contrast was degraded. Meanwhile, if the driving waveforms shown in FIG. 2 are used, the intensity of the discharge generated in all the cells in the reset period can be reduced, and the display contrast can be enhanced.
As described above, since the same voltage is always applied to the X electrodes, the X electrode drive circuit 11 drives all the X electrodes in common. On the other hand, since the scan pulses have to be separately applied to the Y electrodes, the Y electrode drive circuit 12 is provided with a scan driver for applying the voltage separately to each Y electrode and a circuit for supplying various voltages to the power supply terminals of the scan driver. Similarly, since the voltage has to be individually applied to each address electrode, the address electrode drive circuit 13 is provided with a parallel driver for individually applying the voltage to each address electrode and a circuit for supplying a predetermined voltage to the power supply terminals of the parallel driver.
As described above, the present invention relates to the drive circuit of the electrodes to which the scan pulses are applied. More specifically, it relates to the improvement of the Y electrode drive circuit.
FIG. 3 is a diagram showing the structure of the Y electrode drive circuit 12 which applies the voltage to the Y electrodes in accordance with the driving waveforms of FIG. 2 in the PDP device of FIG. 1. The part denoted by a reference character Sn is a part of the scan driver, which corresponds to a sub-driver for driving one Y electrode. The scan driver is provided with as many sub-drivers as the Y electrodes to be driven, and the high potential side power supply terminals VDH and the low potential side power supply terminals VDL of all the sub-drivers are connected in common, respectively. The other portions of FIG. 3 supply the voltage in accordance with the operation to the high potential side power supply terminals VDH and the low potential side power supply terminals VDL of the sub-drivers in common.
More specifically, the sub-driver Sn has first and second switching elements SW1 and SW2 connected in series, a first diode D1 connected in parallel with the first switching element SW1, and a second diode D2 connected in parallel with the second switching element SW2. The low potential side power supply terminal of the first switching element SW1 and the high potential side power supply terminal of the second switching element SW2 are connected to each other and the connecting node thereof is connected to each Y electrode. The high potential side power supply terminal VDH of the first switching element SW1 is connected to the high potential side power supply terminal VDH of the first switching element SW1 of other sub-drivers in common. Further, the low potential side power supply terminal VDL of the second switching element SW2 is connected to the low potential side power supply terminal VDL of the second switching element SW2 of other sub-drivers in common. In the description below, the high potential side power supply terminal VDH of the first switching element SW1 of the sub-driver Sn is referred to as a high potential side power supply terminal VDH of a sub-driver, and the low potential side power supply terminal VDL of the second switching element SW2 of the sub-driver Sn is referred to as a low potential side power supply terminal VDL of a sub-driver.
The high potential side power supply terminal VDH of a sub-driver is connected to the power supply of the voltage Vsc.
The low potential side power supply terminal VDL of a sub-driver is connected to the power supply of the voltage +Vs via a switch SW3 and a diode D3. The connecting node between the switch SW3 and the diode D3 is connected to the ground GND via a capacitor C1 and a switch SW6. The connecting node between the capacitor C1 and the switch SW6 is connected to the power supply of a voltage Vs via a switch SW5 and a resistor R1.
The low potential side power supply terminal VDL of a sub-driver is connected to the power supply of the voltage −Vs via a switch SW4 and a diode D4. A switch SW9 and a resistor R2 connected in series are provided in parallel with the switch SW4. The connecting node between the switch SW4 and the diode D4 is connected to the ground GND via a capacitor C3 and a switch SW8. The connecting node between the capacitor C3 and the switch SW8 is connected to the power supply of a voltage V2 via a capacitor C2 and a switch SW7. The connecting node between the capacitor C2 and the switch SW7 is connected to the ground GND via a switch SW10.
Switches SW1 to SW10 are realized by power MOSFETs, IGBTs and the like.
Hereinafter, the operation at the time of applying the driving waveforms of FIG. 2 by a conventional Y electrode drive circuit 12 of FIG. 3 will be described.
When applying reset write pulses in the reset period, the switch SW6 is turned on and the capacitor C1 is charged with the voltage Vs (90V). Thereafter, in the state where the switch SW6 is turned off, the switches SW3 and SW5 are turned on. In this manner, the voltage of one terminal of the capacitor C1 changes from the GND to V1 (210V), and therefore, the voltage of one terminal of the capacitor C1 is increased to V1+Vs (210V+90V=300V), and the voltage V1+Vs is supplied to the Y electrode Yn via the switch SW3 and the diode D2. The dotted line in FIG. 3 shows a current path at this time. Since the current path is provided with the resistor R1, the voltage of Y electrode Yn gradually increases.
FIG. 4 shows the current path at the time of applying the reset erase pulse. When the reset erase pulse is applied, the switches SW2 and SW9 are turned on. In this manner, the Y electrode Yn is connected to the power supply of the voltage −Vs via the switches SW2 and SW9 and the diode D4. Since the current path is provided with the resistor R2, the voltage of the Y electrode Yn gradually decreases. At this time, the switches SW7 and SW8 are kept turned on.
In the reset period, the capacitor C2 is charged with the voltage V2, and the capacitor C3 is charged with the voltage Vs. When the switches SW7 and SW8 are turned off and the switch SW10 is turned on in the address period, the voltage of the connecting node between the switch SW4 and the capacitor C3 becomes −Vy (−(V2+Vs)). When the switches SW3 and SW9 are turned off and the switch SW4 is turned on, the voltage −Vy is supplied to the low potential side power supply terminal VDL of a sub-driver. The voltage Vsc is supplied to the high potential side power supply terminal VDH of a sub-driver. When the scan pulse is not applied, the switch SW1 is turned on and the switch SW2 is turned off, and when the scan pulse is applied, the switch SW1 is turned off and the switch SW2 is turned on.
In the sustain period, in the state where the switches SW2, SW6 and SW8 are turned on, the switches SW3 and SW4 are alternately turned on, thereby alternately supplying the voltages +Vs and −Vs.